********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Sep 01, 2014
*ECN S14-1752, Rev. C
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7846DP 4 1 2
M1  3 1 2 2 NMOS W=3790552u L=0.50u 
M2  2 1 2 4 PMOS W=3790552u L=0.50u
R1  4 3     RTEMP 36E-3
CGS 1 2     1010E-12
DBD 2 4     DBD
******************************************************************** 
.MODEL  NMOS        NMOS ( LEVEL  = 3               TOX    = 10E-8
+ RS     = 6.3E-3          RD     = 0               NSUB   = 1.52E17   
+ KP     = 3E-5            UO     = 650             
+ VMAX   = 0               XJ     = 5E-7            KAPPA  = 10E-1
+ ETA    = 1E-4            TPG    = 1  
+ IS     = 0               LD     = 0                             
+ CGSO   = 0               CGDO   = 0               CGBO   = 0 
+ TLEV   = 1               BEX    = -1.5            TCV    = 4.6E-3
+ NFS    = 0.8E12          DELTA  = 0.1)
******************************************************************** 
.MODEL  PMOS        PMOS ( LEVEL  = 3               TOX    = 10E-8
+NSUB    = 0.8E16          TPG    = -1)   
******************************************************************** 
.MODEL DBD D (CJO=700E-12 VJ=0.38 M=0.38 
+RS=0.01 FC=0.1 IS=1E-12 TT=3.15E-8 N=1 BV=150.5)
******************************************************************** 
.MODEL RTEMP R (TC1=7.4E-3 TC2=5.5E-6)
******************************************************************** 
.ENDS
 
